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Input :
[V0] [V1] [V2] [V3] [V4] [V5] [V6] [V7] [V8] [V9] [V10] [V11] [V12] [V13] [V14] [V15]
uint8_t Head = 0xFF
uint8_t Tail = 0xFF
[CNT0][NXT0] ... [CNT15][NXT15]
Output :
[sorted] , [length]
Code :
bool FindEntry( uint8_t *pret) {
for(int i=0;i<16;i++) if(cnt[i]) { *pret = i; return true; }
return false;
}
void LinkObjs() {
uint8_t prevIdx = idxEntry;
for(int i=idxEntry+1; i<16; i++) { if(cnt[i]) { nxt[prevIdx] = i; prevIdx = i; } }
idxTail = prevIdx;
}
1. FindEntry(), if failed > nothing to sort
2. LinkObjs(), if idxTail == idxHead > single component
3. SortCycle()
Testcases
1) All zero
2) Single component
3) Two components sort
4) Multiple components sort
5) Full spectrum components sort
1001 Reserved 9X
1000 Reserved 8X
8x8 = 64
5, 10, 15, 12, 8, 14
(00) 05 (01) 10 (02) 15 (03) 12 (04) 08 (05) 14 06) 00 07) 00 08) 00 09) 00 10) 00 11) 00 12) 00 13) 00 14) 00 15) 00
(01) 10 (02) 15 (03) 12 (04) 08 (05) 14 (00) 05 06) 00 07) 00 08) 00 09) 00 10) 00 11) 00 12) 00 13) 00 14) 00 15) 00
(02) 15 (03) 12 (01) 10 (05) 14 (04) 08 (00) 05 06) 00 07) 00 08) 00 09) 00 10) 00 11) 00 12) 00 13) 00 14) 00 15) 00
(02) 15 (03) 12 (05) 14 (01) 10 (04) 08 (00) 05 06) 00 07) 00 08) 00 09) 00 10) 00 11) 00 12) 00 13) 00 14) 00 15) 00
(02) 15 (05) 14 (03) 12 (01) 10 (04) 08 (00) 05 06) 00 07) 00 08) 00 09) 00 10) 00 11) 00 12) 00 13) 00 14) 00 15) 00
(02) 15 (05) 14 (03) 12 (01) 10 (04) 08 (00) 05 06) 00 07) 00 08) 00 09) 00 10) 00 11) 00 12) 00 13) 00 14) 00 15) 00
15 14 12 10 8 5
0111 STACK Instructions
0x70 0111.0000 PUSH <SRC>
0x71 0111.0001 POP <DST>
0x72 0111.0010 PUSHM <SRC> <count>
0x73 0111.0011 POPM <DST> <count>
0x74 0111.0100 PUSHF
0x75 0111.0101 POPF
0110 JMP / CALL Instructions
0x60 0110.0000 R-CALL <C8> ; +/-
0x61 0110.0001 D-CALL <C16> ; Direct Call
0x62 0110.0010 S-CALL <SRC> ; Addr Call
0x63 0110.0011 L-CALL <CS> <IP> ; Long Call
0x60 0110.0000 R-JMP <C8> ; Jump +/- 127
0x61 0110.0001 D-JMP <C16> ; Direct Jump
0x62 0110.0010 S-JMP <SRC> ; Addr Jump
0x63 0110.0011 L-JMP <CS> <IP> ; Long Jump
0101 MATH
0x50 0101.0000 <SRC=DST> INC ; Increment
0x51 0101.0001 <SRC=DST> DEC ; Decrement
0x52 0101.0010 <SRC=DST> - ; Removed INV
0x53 0101.0011 <SRC=DST> - ; Removed CLR
0x54 0101.0100 <SRC=DST> -
0x55 0101.0101 <SRC=DST> -
0x56 0101.0110 <SRC=DST> -
0x57 0101.0111 <SRC=DST> -
0x58 0101.1000 <DST> <SRC> ; ADD ; DST += SRC
0x59 0101.1001 <DST> <SRC> ; ADDC ; DST += SRC `
0x5A 0101.1010 <DST> <SRC> ; SUB ; SUB -= SRC
0x5B 0101.1011 <DST> <SRC> ; SUBC ; SUB -= SRC `
0x5C 0101.1100 <DST> <SRC1> <SRC2> ; ADD DST = SRC1 + SRC2
0x5D 0101.1101 <DST> <SRC1> <SRC2> ; ADDC DST = SRC1 + SRC2 `
0x5E 0101.1110 <DST> <SRC1> <SRC2> ; SUB DST = SRC1 - SRC2
0x5F 0101.1111 <DST> <SRC1> <SRC2> ; SUBC DST = SRC1 - SRC2 `
0100 LOGIC Instructions
0x40 0100 x000 <DST> <SRC> AND
0x41 0100 x001 <DST> <SRC> OR
0x42 0100 x010 <DST> <SRC> XOR
0x43 0100 x011 -
0x44 0100 x100 AND3 <DST> <SRC1> <SRC2> ; DST = SRC1 & SRC2
0x45 0100 x101 OR3 <DST> <SRC1> <SRC2> ; DST = SRC1 | SRC2
0x46 0100 x110 XOR3 <DST> <SRC1> <SRC2> ; DST = SRC1 ^ SRC2
0x47 0100 x111 -
0011 MEMMOV Move memory block
0011 df00 MEMMOVB <CNT> ; [DS:DP] > [ES:EP] d - DP up / down f - EP up / down cnt=CR
0011 df01 MEMMOVW <CNT> ; [DS:DP] > [ES:EP] d - DP up / down f - EP up / down cnt=CR
0011 df10 MEMMOVWsw <CNT> ; [DS:DP] > [ES:EP] d - DP up / down f - EP up / down cnt=CR
0011 df11 -
0010 MEMBLK
0010.0000 FILLB <SRC> ; Fill bytes [ES:EP] cnt=CR
0010.0001 FILLW <SRC> ; Fill words [ES:EP] cnt=CR
0010.0010 MEMSCAN <VAL> <CNT>
0001 MOV
0001.eqqq MOV <SRC> , <DST> ; Bytes count from 1+2+2 to 1+3+3 [ 5:7 ]
eqqq Flags conditions, e - enabled, N - invert
eN00 If Zero
eN01 If Negative
eN10 If Overflow
eN11 If Carry
eN00 If Not Zero
eN01 If Not Negative
eN10 If Not Overflow
eN11 If Not Carry
0000 Interrupts
0x00 0000.0000 CLI
0x01 0000.0001 SEI
0x02 0000.0010 -
0x03 0000.0011 RETI
0x04 0000.0100 -
0x05 0000.0101 -
0x06 0000.0110 -
0x07 0000.0111 RET
0x08 0000.1000 -
0x09 0000.1001 -
0x0A 0000.1010 -
0x0B 0000.1011 -
0x0C 0000.1100
0x0D 0000.1101
0x0E 0000.1110
0x0F 0000.1111 RETL
---------------------------------------------------
mm Mode
---------------------------------------------------
00 Constant
01 Register
10 Reserved
11 Memory
---------------------------------------------------
oo Order
---------------------------------------------------
W16
W16rev
H8
L8
---------------------------------------------------
ss Segment
---------------------------------------------------
ss = 00 CS
ss = 01 DS
ss = 10 ES
ss = 11 SS
---------------------------------------------------
i = inverted bit
---------------------------------------------------
---------------------------------------------------
Addressing mode : <SRC> / <DST>
---------------------------------------------------
00i0.xxxx DDDD.DDDD 8-bit constant
00i1.xxxx DDDD.DDDD DDDD.DDDD 16-bit constant
01ix.xxoo rrrr.rrrr register
10ix.xxoo rrrr.rrrr extended register
11ss.00oo DDDD.DDDD Memory @ ss:[C8]
11ss.01oo rrrr.rrrr Memory @ ss:[rr]
11ss.10oo rrrr.rrrr DDDD.DDDD Memory @ ss:[rr+C8]
11ss.11oo yyyy.yyyy I/O Port Nr#
MCU#1
registers: 256 x 16-bit + CS:IP + DS:DP + ES:EP + SS:SP + FR
MCU#2
registers: 256 x 16-bit + CS:IP + DS:DP + ES:EP + SS:SP + FR
--------------------------------
Segment registers
--------------------------------
000 CS
001 DS
010 ES
011 SS
--------------------------------
Pointer registers
--------------------------------
100 IP Instruction pointer
101 DP Src pointer
110 EP Dst pointer
111 SP Stack pointer
--------------------------------
FLAGS Register
--------------------------------
0 Z | Zero
1 N | Negative
2 O | Overflow
3 P | Parity
4 - |
5 - |
6 - |
7 I | Interrupt
--------------------------------
Opcodes list
--------------------------------
0000 INT
0001 MOV
0010 MEMSET
0011 MEMMOV
0100 LOGIC
0101 MATH
0110 JMP / CALL
0111 STACK
1000 -
1001 -
1010 -
1011 -
1100 -
1101 -
1110 -
1111 -
AX : 16
BX : 16
CX : 16
DX : 16
CS:IP
DS
ES
SS:SP
Memory space : 24-bit A2 A1 A0 / 16MB x 8
0000.0000 nop
0000.0001 ret
0000.0010 iret
0000.0011 halt
0000.0100
0000.0101
0000.0110
0000.0111 EXT-MAP
0000.1000
0000.1001
0000.1010
0000.1011
0000.1100
0000.1101
0000.1110 SETBLK
0000.1111 MVBLK
0001 00rr inc
0001 01rr dec
0001 10rr inv
0001 11rr swphl
0010 00rr shl
0010 01rr shr
0010 10rr -
0010 11rr -
0011 00rr -
0011 01rr -
0011 10rr -
0011 11rr -
0100 ABCD push ax bx cx dx
0101 ABCD pop ax bx cx dx
0110 ++++ push DS ES SS
0111 ++++ pop DS ES SS
inb
inw
outb
outw
1000 rryy and
1001 rryy or
1010 rryy xor
1011 rryy swap
1000 rryy add
1001 rryy adc
1010 rryy sub
1011 rryy subc
E0 : 1110 000n mmmm.mmmm jz jnz
E2 : 1110 001n mmmm.mmmm ja jna
E4 : 1110 010n mmmm.mmmm jb jnb
E6 : 1110 011n mmmm.mmmm zn jnn
E8 : 1110 100n mmmm.mmmm -
EA : 1110 101n mmmm.mmmm -
EC : 1110 110n mmmm.mmmm -
EE : 1110 111n mmmm.mmmm -
Init
F0 : 1111 0000 memrbl
F1 : 1111 0001 memrbh
F2 : 1111 0010 memr16
F3 : 1111 0011 memr16s
F4 : 1111 0100 memwbl
F5 : 1111 0101 memwbh
F6 : 1111 0110 memww
F7 : 1111 0111 memwws
F8 : 1111 10rr v16 Init AX : V16
F9 : 1111 10rr v16 Init BX : V16
FA : 1111 10rr v16 Init CX : V16
FB : 1111 10rr v16 Init DX : V16
FC : 1111 1100 -
FD : 1111 1101 -
FE : 1111 1110 a16 ljmp
FF : 1111 1111 a16 lcall
16bit = 64K
17bit = 128K
Regs : 256 x 16 bit
RAM : 256 x 16 bit
A+B>C
0x00 0000 . 0000 NOP
0x01 0000 . 0001 RET
0x02 0000 . 0010 IRET
0x03 0000 . 0011 LRET
0x04 0000 . 0100 -
0x05 0000 . 0101 -
0x06 0000 . 0110 -
0x07 0000 . 0111 -
0x08 0000 . 1000 -
0x09 0000 . 1001 -
0x0A 0000 . 1010 -
0x0B 0000 . 1011 -
0x0C 0000 . 1100 -
0x0D 0000 . 1101 -
0x0E 0000 . 1110 -
0x0F 0000 . 1111 -
; -------------------------
; 2-bytes commands
; -------------------------
; Math
0x20 0010 . 0000 RRRR.RRRR CLR ; Clear Register
0x21 0010 . 0001 RRRR.RRRR ONE ; Set Register to 1
0x22 0010 . 0010 RRRR.RRRR MONE ; Set Register to -1
0x23 0010 . 0011 RRRR.RRRR INV ; Invert
0x24 0010 . 0100 RRRR.RRRR INC ; Increment +1
0x25 0010 . 0101 RRRR.RRRR DEC ; Decrement -1
0x26 0010 . 0110 RRRR.RRRR NBL8 ; High8<>Low8
0x27 0010 . 0111 RRRR.RRRR NBL4 ; High4<>Low4
; Stack related
0x28 0010 . 1000 . RRRRRRRR push <R> ; Push register to stack
0x29 0010 . 1001 . RRRRRRRR pop <R> ; Pop register from stack
0x2A 0010 . 1010 . RRRRRRRR - ;
0x2B 0010 . 1011 . RRRRRRRR - ;
0x2C 0010 . 1100 . RRRRRRRR - ;
0x2D 0010 . 1101 . RRRRRRRR - ;
0x2E 0010 . 1110 . RRRRRRRR - ;
0x2F 0010 . 1111 . RRRRRRRR - ;
; Bit Shift
0x30 0011 . 1010 . RRRRRRRR SHL ; Shift left
0x31 0011 . 1011 . RRRRRRRR SHR ; Shift right
0x32 0011 . 1100 . RRRRRRRR - ;
0x33 0011 . 1101 . RRRRRRRR - ;
0x34 0011 . 1110 . RRRRRRRR - ;
0x35 0011 . 1111 . RRRRRRRR - ;
; Branch Short
0x40-41 0100 . 000N aaaa.aaaa JA / JNA ; A>B ? A<=B ?
0x42-43 0100 . 001N aaaa.aaaa JB / JNB ; A<B ? A>=B ?
0x44-45 0100 . 010N aaaa.aaaa JE / JNE ; A=B ? A<>B ?
0x46-47 0100 . 011N aaaa.aaaa JZ / JNZ ; A=0 ? A!=0 ?
0x60 0110 . 0000 aaaa.aaaa RJMP ; Relative jump +/- 127
0x61 0110 . 0001 aaaa.aaaa RCALL ; Relative call +/- 127
; -------------------------
; 3-bytes commands
; -------------------------
; Logic
0x80 1000 . 0000 RRRR.RRRR YYYY.YYYY AND ; R&=Y
0x81 1000 . 0001 RRRR.RRRR YYYY.YYYY OR ; R|=Y
0x82 1000 . 0010 RRRR.RRRR YYYY.YYYY XOR ; R^=Y
0x83 1000 . 0011 RRRR.RRRR YYYY.YYYY COPY ; R=Y
0x84 1000 . 0100 RRRR.RRRR YYYY.YYYY ADD ; R+=Y
0x85 1000 . 0101 RRRR.RRRR YYYY.YYYY SUB ; R-=Y
0x86 1000 . 0110 RRRR.RRRR YYYY.YYYY CMP ; R-Y > FLAGS
0x87 1000 . 0111 RRRR.RRRR YYYY.YYYY SWAP ; R<>Y
0x88 1000 . 1000 RRRR.RRRR YYYY.YYYY
0x89 1000 . 1001 RRRR.RRRR YYYY.YYYY
0x8A 1000 . 1010 RRRR.RRRR YYYY.YYYY
0x8B 1000 . 1011 RRRR.RRRR YYYY.YYYY
0x8C 1000 . 1100 RRRR.RRRR YYYY.YYYY
0x8D 1000 . 1101 RRRR.RRRR YYYY.YYYY
0x8E 1000 . 1110 RRRR.RRRR YYYY.YYYY
0x8F 1000 . 1111 RRRR.RRRR YYYY.YYYY
0x90 1001 . 0000 RRRR.RRRR MMMM.MMMM RMEM
0x91 1001 . 0001 RRRR.RRRR MMMM.MMMM WMEM
0x92 1001 . 0010 RRRR.RRRR MMMM.MMMM RMEMSW
0x93 1001 . 0011 RRRR.RRRR MMMM.MMMM WMEMSW
0x94 1001 . 0100 RRRR.RRRR MMMM.MMMM RMEML
0x95 1001 . 0101 RRRR.RRRR MMMM.MMMM WMEML
0x96 1001 . 0110 RRRR.RRRR MMMM.MMMM RMEMH
0x97 1001 . 0111 RRRR.RRRR MMMM.MMMM WMEMH
0xF0 1111 . 0000 AAAA.AAAA AAAA.AAAA JMP
0xF1 1111 . 0001 AAAA.AAAA AAAA.AAAA CALL
0xF8 1111 . 1000 AAAA.AAAA AAAA.AAAA AAAA.AAAA LJMP
0xF9 1111 . 1001 AAAA.AAAA AAAA.AAAA AAAA.AAAA LCALL
R252 [DS]
R253 [DP]
R254 [CS]
R255 [PC]
Regs : 256 x 16 bit
RAM : 256 x 16 bit
A+B>C
0000 . 0000 NOP
---- ---- RET
---- ---- IRET
---- ---- LRET
; Pointers related
0000 . 0001 . RRRRRRRR setp a
0000 . 0010 . RRRRRRRR setp b
0000 . 0011 . RRRRRRRR setp c
; Stack related
0000 . 0100 . RRRRRRRR push <R> ; Push register to stack
0000 . 0101 . RRRRRRRR pop <R> ; Pop register from stack
; Math
0001 . 0000 CLR [C]; Clear C
0001 . 0001 ONE [C]; Set C=1
0001 . 0010 INC [C]; Increment +1 C
0001 . 0011 DEC [C]; Decrement -1 C
0001 . 0100 ADD ; A+B=C
0001 . 0101 SUB ; A-B=C
; Bitwise
0001 . 0100 SHL [C] ; Shift left C
0001 . 0101 SHR [C] ; Shift right C
0001 . 0110 INV [C] ; Invert C
0001 . 0111 ----
; Logic
0000 . 1100 AND ; A&B => C
0000 . 1101 OR ; A|B => C
0000 . 1110 XOR ; A^B => C
0000 . 1111 MOV ; A => C
; Branch
0011 . XXXX JA, JNA A>B ? A<=B ?
0011 . XXXX JB, JNB A<B ? A>=B ?
0011 . XXXX JE, JNE A=B ? A<>B ?
0011 . XXXX JZ, JNZ A=0 ? A!=0 ?
1111 . JMP
1111 . CALL
1111 . LJMP
1111 . LCALL
R252 DS:
R253 DC
R254 CS:
R255 PC
CODE-RAM : 8Mb
DATA-RAM : 8Mb
Regs: 32 x 16bit
0 ) 0000 0000 . 0000 0000 NOP
1 ) 0000 0000 . 0000 0001 HLT
2 ) 0000 0000 . 0000 0010 RET
3 ) 0000 0000 . 0000 0011 IRET
4) 0000 0000 . 0000 0100 LRET
4 ) 0000 0001 . 000R RRRR CLR
4 ) 0000 0001 . 001R RRRR NEG
5 ) 0000 0001 . 010R RRRR INC
6 ) 0000 0001 . 011R RRRR DEC
7 ) 0000 0001 . 100R RRRR -
7 ) 0000 0001 . 101R RRRR -
7 ) 0000 0001 . 110R RRRR -
7 ) 0000 0001 . 111R RRRR -
8 ) 0000 0000 . SHL1
8 ) 0000 0000 . SHL2
8 ) 0000 0000 . SHL4
8 ) 0000 0000 . SHL8
8 ) 0000 0000 . SHR1
8 ) 0000 0000 . SHR2
8 ) 0000 0000 . SHR4
8 ) 0000 0000 . SHR8
9 ) 0000 0000 101R RRRR XOR
10 ) 0000 0000 110R RRRR OR
11 ) 0000 0000 111R RRRR AND
12) 0001 0MYY YYYR RRRR ADD
13) 0001 1MYY YYYR RRRR SUB
9 ) 0000 0000 . SWAP
14) MEM_RDB
15) MEM_WRB
14) MEM_RDW
15) MEM_WRW
16) IN
17) OUT
19) 0100 00YY . YYYR RRRR COPY
PUSH
POP
18) 1100 AAAA AAAA AAAA JMP
19) 1101 AAAA AAAA AAAA CALL
20) 1110 AAAA AAAA AAAA LJMP
21) 1111 AAAA AAAA AAAA LCALL
1000 000N AAAA AAAA JZ, JNZ
1000 001N AAAA AAAA JE, JNE
1000 010N AAAA AAAA JA, JNA
1000 011N AAAA AAAA JB, JNB
1000 100N AAAA AAAA JM, JNM
R0 :
R1 :
R2 :
R3 :
R4 :
R5 :
R6 :
R7 :
R8 :
R9 :
R10 :
R11 :
R12 :
R13 :
R14 :
R15 :
R16 :
R17 :
R18 :
R19 :
R20 :
R21 :
R22 :
R23 :
R24 : SS Stack Segment , 16-bit
R25 : SP Stack Pointer , 16-bit
R26 : DS Data Segment , 16-bit
R27 : DC Data Counter , 16-bit
R28 : ES Data Segment , 16-bit
R29 : EC Data Counter , 16-bit
R30 : CS Code Segment , 16-bit
R31 : PC Program Counter , 16-bit
O, Z, N
# adduser username
# usermod -aG sudo username
4 2-bit
8 3-bit
16 4-bit
32 5-bit
64 6-bit
128 7-bit
256 8-bit
512 9-bit
1024 10-bit
2048 11-bit
4096 12-bit
13-bit 8K
14-bit 16K
15-bit 32K
16-bit 64K
17-bit 128K
18-bit 256K
19-bit 512K
20-bit 1M
21-bit 2M
22-bit 4M
23-bit 8M
24-bit 16M
32 bit slot [X]:[Y]:[W,H,A]
X: 12 bit (0 ... 4095)
Y: 12 bit (0 ... 4095)
W: 3-bit 2^(n+1)
H: 3-bit 2^(n+1)
A: 2-bit H-Flip, V-Flip
0 - 2 pix
1 - 4 pix
2 - 8 pix
3 - 16 pix
4 - 32 pix
5 - 64 pix
6 - 128 pix
7 - 256 pix
Другая возможность - создать файл правил в /etc/udev/rules.d/каталоге. У меня была похожая проблема, и я создал 50-myusb.rulesфайл в указанном выше каталоге с таким содержанием:
KERNEL=="ttyACM[0-9]*",MODE="0666"
Обратите внимание, что это даст любому устройству, подключенному к сокету ttyACM права на чтение / запись. Если вам нужно только определенное устройство для получения разрешений на чтение / запись, вы также должны проверить idVendorи idProduct. Вы можете найти их, выполнив lsusbкоманду дважды: один раз, когда ваше устройство не подключено, и один раз, когда оно подключено, а затем просмотрите дополнительную строку на выходе. Там вы увидите нечто подобное Bus 003 Device 005: ID ffff:0005. В этом случае idVendor = ffffи idProduct = 0005. Твой будет другим. Чем вы изменяете файл правил:
ACTION=="add", KERNEL=="ttyACM[0-9]*", ATTRS{idVendor}=="ffff", ATTRS{idProduct}=="0005", MODE="0666"
Теперь только это устройство получает разрешения. Прочтите это, чтобы узнать больше о написании правил udev.
* PALETTE *
Build-in 256 Colors Palette
* FSMC Interface *
Параллельный доступ к памяти, 16-бит.
Address bus: A[18:0]
Data bus: D[15:0]
STM32F407
PORTD PD4 FSMC_NRD Read enable
PORTD PD5 FSMC_NWR Write enable
PORTD PD7 FSMC_NCE Chip enable
PORTB PB7 FSMC_NALE Address valid
> file : tree item
> name : file name
> addr : value or "auto" if missed
> * offset - optional
> * length - optional
{
"file" : { "name": "boot.bin", "addr" : 0, "offset" : 0, "length" : 1024 },
"file" : { "name": "mcu1.bin", "addr" : "auto", "offset" : 0, "length" : 32K },
"file" : { "name": "mcu2.bin", "addr" : "auto", "offset" : 0, "length" : 32K }
}